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Virage Logic Supports TSMCs Power Trim Service

http://www.tradingmarkets.com/.site/news/Stock%20N [2008-6-10]


TSMC s Power Trim Service overlays manufacturing design technologysoftware and advanced semiconductor process technology to tunemanufacturing chip design. The Power Trim compliant Virage Logic IPcan enable power leakage reduction through TSMC s Power TrimService without area penalties, while maintaining chip performance,the Virage Logic said.
Virage Logic was the first commercial IP provider to release its40-nanometer (nm) SiWare product portfolio on TSMC s 40nmmanufacturing process with memory compilers and logic libraries.Virage Logic now is also the first commercial IP provider tosupport TSMC s Power Trim Service, announced at the TSMC symposiumin April.
Virage Logic stated that it extends the inherent power-managementbenefits of SiWare IP to cover TSMC 65nm and 90nm process nodeswhile offering early access to design more competitive chips withreduced leakage power and significant cost savings. With itsadvanced tradeoff capabilities, SiWare Memory users can achievestatic power savings of up to 35 percent, 70 percent or 90 percentdepending on their selection of the built-in light sleep, deepsleep and shut-down modes available in 40nm memories.
Being first to market with commercial IP tailored for the PowerTrim Service reflects our close collaboration with TSMC to supportadvanced manufacturing processes, said Brani Buric, vice presidentof product marketing and strategic foundry relationships, VirageLogic. For more than a year, Virage Logic has been a TSMC earlydevelopment partner at 40nm. We re honored to build on our trustedpartnership to address the SoC design community s need for lowpower solutions that meet the stringent demands of advancedgeometries and help them proceed with confidence to the nextprocess node.
It s the designer who benefits most, said S.T. Juang, seniordirector of design infrastructure marketing at TSMC. With VirageLogic s SiWare 40nm IP supporting our Power Trim Service, designersenjoy the benefits of low-power design optimization at the 40nmprocess technology.
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((Distributed via M2 Communications Ltd - http://www.m2.com))

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