Si2 Announces Release of Common Power Format Version 1.1

Tag : power tools
Today the Silicon Integration Initiative (Si2) announced release ofthe Common Power Format (CPF) Version 1.1, incorporating majorenhancements to the widely adopted low-power intent format. CPF 1.1was approved by the Low Power Coalition (LPC).

Ameesh Desai, Si2 Board Chair and Senior Director of Design Toolsand Methodology at LSI said, "I am pleased with the rapid progressof the CPF. Efficient power utilization has become a primary needfor electronic products worldwide. The efforts by Si2's LPCcoalition members are enabling the industry to implement low-powersemiconductors that reduce costs and risks and development times."

The CPF standard reduces this risk by extending the industry'sRTL-GDSII design infrastructure to support low power designtechniques in a safe and efficient manner. In a little over a yearthe LPC has taken the next step to broaden the applicability to aneven larger set of designs and methodologies with CPF 1.1.

CPF is a Tcl-based format used to capture the power intent of adesign. CPF complements the RTL and/or netlist description of thedesign allowing existing golden RTL blocks to be used withoutmodification. CPF has achieved wide acceptance in EDA tools inend-user tool flows, and enjoys a record of numerous completed chiptape-outs with subsequent testimonials, and adoption into leadingfoundry reference flows.

The extensions in CPF 1.1 further expand support for bottom-up andtop-down hierarchical flows and enable the integration, reuse andverification of internal and 3rd party developed power aware IP.Power intent for multiple IP blocks from multiple sources can beintegrated together with appropriate resolution of power domains,power modes and power related rules. In addition, CPF 1.1 supportssophisticated macro modeling of hard IP such as embedded memorieswith complex power structures. This enables implementation andverification of the IP's power behaviors in the design context.

CPF 1.1 expands the number of power domain operating states toinclude reversed biased and forward biased states. This enables thesupport of additional sophisticated power minimization techniquesthat are becoming more common in low power designs. CPF 1.1improves the modeling of transitions between power modes whichenables in-depth verification to ensure that the design cansuccessfully enter and exit each operating mode, preventing acommon source of failure in low power designs. CPF 1.1 alsoprovides a new general model to describe power requirements forspecial low power cells such as state retention, isolation,"always-on" cells. This improves designer productivity by furtherautomating implementation and verification of the design powerintent.

Gill Watt, CAD Manager at AMD, and chair of the LPC said, "The LPCmembers recognize that the marketplace is demanding more powerefficient designs for both mobile and wired products. CPF 1.1contains major enhancements to extend its applicability to newdesign styles and methodologies. These enhancements provide greaterflexibility particularly for designs that re-use IP from multiplesources. This flexibility is expected to expand the use ofpower-aware techniques from specialized power-critical designs intowidespread practices used in all mainstream designs, allowing LPCmember companies to provide more power efficient products to themarketplace."

CPF 1.1 is available for download at: http://www.si2.org/?page=811.

Background

The CPF standard was approved and made publicly available in Marchof 2007. CPF is supported by many adoption aids and tools, allavailable from Si2: a CPF tutorial (in both English and Mandarin),a CPF Parser software, the CPF Pocket Guide, a LPC Glossary. A CPFRelational Analyzer is available to LPC members. CPF is supportednot only by the Low Power Coalition, but also the Power ForwardInitiative, http://www.powerforward.org.

About the Low Power Coalition (LPC)

The Low-Power Coalition (LPC) is delivering enhanced capabilitiesin low-power Integrated Circuit (IC) design flows in particularrelating to specifications of low-power design intent,architectural tradeoffs, logical/physical implementation, designverification and testability. Member companies are: Advanced MicroDevices (NYSE: AMD), ARM (Nasdaq: ARMHY), Atrenta, Azuro, CadenceDesign Systems (Nasdaq: CDNS), Calypto Design Systems, ChipVisionDesign Systems, Entasys, Envis, Freescale Semiconductor, GlobalUnichip, IBM (NYSE: IBM), Intel (Nasdaq: INTC), LSI Corporation(NYSE: LSI), NXP Semiconductors, Sequence Design, and Virage Logic(Nasdaq: VIRL). The Low Power Coalition is an open industry groupoperating under the auspices of Si2. All interested parties areinvited to join existing LPC members and participate. For furtherinformation on the Low Power Coalition, seehttp://www.si2.org/?page=726.

About Si2

Si2 is an organization of industry-leading semiconductor, systems,EDA, and manufacturing companies focused on improving the wayintegrated circuits are designed and manufactured in order to speedtime to market, reduce costs, and meet the challenges of sub-microndesign. Si2 is uniquely positioned to enable collaboration througha strong implementation focus driven by its member companies. Si2focuses on developing practical technology solutions to industrychallenges. Si2 represents nearly 100 companies involved in allparts of the silicon supply chain throughout the world. Web site:www.si2.org.