New Lattice Mixed Signal Software Design Tool Supports Automotive ...

Tag : Power Tools
-- All Power Manager and ispClock Devices Also Supported --

HILLSBORO, OR - AUGUST 18, 2008 - Lattice Semiconductor (NASDAQ:LSCC) today announced the release of its PAC-Designer®software design tool suite, version 4.99a. The tool suite nowsupports Lattices AECQ100-qualified automotive Power Manager II(LA-ispPAC®-POWR1014/A) devices. The PAC-Designer tool suitealso provides easy to use, point-and-click, intuitive design andverification support for all Power Manager and ispClock™mixed signal devices.

“Todays automotive designs use advanced CPUs, FPGAs andASICs, which increases the number of board-mounted powersupplies,” said Stan Kopec, Lattice corporate vice presidentof marketing. “Using Lattices PAC-Designer software tools,designers can quickly implement and fine tune the power managementalgorithm used to control and monitor these diverse power supplies.The resulting board-specific power management design is moreaccurate, requires less circuit board area and costs less thantraditional designs using multiple off-the-shelf dedicateddevices.”

The Benefits of PAC-Designer Software

Common power management functions found on circuit boards includehot-swap control, voltage supervision, supply sequencing and resetgeneration. To ensure board reliability, all board-mounted powersupplies should be sequenced and monitored via a power managementalgorithm. Typically, the power management algorithm is eitherchanged or fine tuned during the board debug process to meetunforeseen device power-up behavior. Traditional solutions arehard-wired and cannot be changed without an expensive boardre-spin. Lattices Windows-based PAC-Designer software enablesimplementation of a new power management algorithm in LatticesPower Manager II devices within minutes.

Similarly, clock network designs require timing adjustments duringthe board debug phase. The Lattice ispClock devices support anin-system programmable skew mechanism. Using the PAC-Designersoftware, designers can precisely alter the clock skew of each ofthe clock nets. Traditionally, clock skew has been implemented by“snaking” clock traces on the board, and any change tothe skew was implemented through a time consuming, expensive boardre-spin. Using the PAC-Designer software, the clock network skew isaltered simply by reprogramming the ispClock device.

Pricing and Availability

The PAC-Designer software is available now and can be downloadedfree of charge from the Lattice website, www.latticesemi.com .

About Lattice Automotive Power Manager II Devices

The Lattice Automotive Power Manager II device family includes theLA-ispPAC-POWR1014 and LA-ispPAC-POWR1014A. The LA-ispPAC-POWR1014device integrates a 24 macrocell PLD and 10 analog voltagemonitoring inputs, each with dual precision voltage monitoringcomparators with an accuracy of 0.3%. In addition, theLA-ispPAC-POWR1014A device integrates a 10-bit Analog to DigitalConverter (ADC) for voltage measurements and an I2C interface thatenables a microcontroller or processor to read the status of allthe comparators, inputs as well as outputs. Both the POWR1014 andPOWR1014A devices have been ruggedized to operate across a widerange of power supply voltages, from 2.8V to 3.9V.

About Lattice ispClock Devices

There are two programmable Lattice ispClock families: theispClock5600A family (in-system programmable zero-delay clockgeneration and distribution) and the ispClock5300S family(in-system programmable zero-delay clock distribution). Users canstandardize on these devices across a wide variety of designsinstead of using a separate set of single-function clock devices oneach board design.

The ispClock5600A devices provide seven on-chip counters for thegeneration of up to 5 clock frequencies. The E2CMOS®-basedispClock5600A device can source up to 20 clock outputs, each withindependently programmable output skew, I/O standard and frequencyselection.

The ispClock5300S devices integrate a zero-delay buffer and fan-outbuffers with independently programmable skew, I/O standard andoutput termination impedance.

About Lattice Semiconductor

Lattice Semiconductor Corporation provides the industrys broadestrange of Programmable Logic Devices (PLD), including FieldProgrammable Gate Arrays (FPGA), Complex Programmable Logic Devices(CPLD), Mixed-Signal Power Management and Clock Generation Devices,and industry-leading SERDES products.

Lattice continues to deliver “More of the Best” to itscustomers with comprehensive solutions for system design, includingan unequaled portfolio of high-performance, non-volatile andlow-cost FPGAs.

Lattice products are sold worldwide through an extensive network ofindependent sales representatives and distributors, primarily toOEM customers in communications, computing, industrial, consumer,automotive, medical and military end markets. For more information,visit www.latticesemi.com

Statements in this news release looking forward in time are madepursuant to the safe harbor provisions of the Private SecuritiesLitigation Reform Act of 1995. Investors are cautioned thatforward-looking statements involve risks and uncertaintiesincluding market acceptance and demand for our new products, ourdependencies on our third party software suppliers, the impact ofcompetitive products and pricing, technological and productdevelopment risks and other risk factors detailed in the CompanysSecurities and Exchange Commission filings. Actual results maydiffer materially from forward-looking statements.

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Lattice Semiconductor Corporation, Lattice (& design), L (&design), ispPAC, ispClock, PAC-Designer, E2CMOS and specificproduct designations are either registered trademarks or trademarksof Lattice Semiconductor Corporation or its subsidiaries in theUnited States and/or other countries.

GENERAL NOTICE: Other product names used in this publication arefor identification purposes only and may be trademarks of theirrespective holders.