IBM challenges TSMC on gate capacitance question at 28 nm

Tag : capacitance

Sep 30 2008 4:28PM | Permalink | Email this | Comments (3) |
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TSMC's roadmap announcement for their 28 nm node yesterday has stirred considerablecontroversy already. The issue is the company's decision to dividetheir process development into two tracks: one to be ready earlyusing SiON gate technology, and one to be ready somewhatlater—and with more schedule risk—usinghigh-k/metal-gate technology.
TSMC justified the decision by claiming that for designs with highduty cycles—meaning that blocks would most of the time beeither operating or power-gated off—active power was moreimportant than leakage power. And hence gate capacitance was a moreimportant factor in energy consumption than leakage. Further, thecompany claimed that their SiON process would have a significantlylower gate capacitance, and hence lower active power, than anequivalent high-k/metal-gate process.
But in comments to a Blog posting describing the announcement, one reader jumped on that claim atonce, pointing out several issues that make the conclusion lessthan obvious. And in remarks during a question-and-answer sessionat the Common Platform Technology Forum today, IBM Semiconductor R/D Center vice president Gary Pattonchallenged the notion that a SiON process would have lower activepower, or for that matter, that it would even have lower gatecapacitance. He said that while the higher k would increase thegate capacitance per unit area, the higher k also allowedtransistors to have a shorter effective channel length, so that thecapacitance stayed about the same. Others have pointed out that thehigh-k transistor would either have the same current at a smallerwidth, so in principle it should have less active gate area, hencelower capacitance, and dissipate less active power at equivalentperformance.
An Steegen, senior technology development manager at IBM Systemsand Technology Group, agreed that gate capacitance—or moreproperly, inversion-layer thickness—is a big deal in thewhole question of process scaling. But she added that you couldn'tjust look at gate capacitance in estimating the active powerdissipation in a circuit—you had to examine the total circuitcapacitance. And once again the smaller minimum dimensions of thehigh-k transistor make a difference. Smaller transistors allow fordenser packing, shortening average wire length between thetransistors and reducing the load capacitance. (Relaxed contactspacing due to the shorter channel length is also a big deal foryield, Steegen suggested, since the contact layer is one of themost critical steps in the process now.)
"This is not just a PowerPoint comparison," Patton said."We have run SiON and high-k/metal-gate devices side by side,and the high-k versions have lower dynamic power." Thus it appears that TSMC may have to defend it's claim that theSiON process track is a benefit to designers, and not a necessarymeans to make up for delays in high-k process integration. Thiscould be an interesting discussion.

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