Using auto-zero comparator techniques to improve PWM performance

Tag : Voltage Regulator Circuit
Comparators are subject to input offset errors that can be eithersystematic or layout related. Two applications of comparators in aPWM controller are detecting when there is no current in theinductor, as well as no current in the main control-loopcomparator. During the discontinuous conduction mode of theconverter, the comparator must detect when the inductor currentreverses through the lower power MOSFET. This is done by comparingthe drain voltage of the MOSFET during its on time to the groundreference.

The use of an auto-zeroing comparator will eliminate the offsetvariation and, therefore, improve the accuracy of the zero-currentdetection. For the main PWM comparator, the use of an auto-zeroingcomparator eliminates the control-loop offset between the erroramplifier and the ramp-crossing level, thereby improving theoverall system performance, especially at duty cycles that are lessthan 5%.

Introduction
Lower power and high efficiency are the key priorities in powermanagement today. Portable electronics need to conserve batterypower and be able to operate over a wide range of input voltages.For PWM voltage regulators designed into portable systems, theserequirements present design challenges as well as opportunities.

Two such opportunities exist for the use of auto-zeroingcomparators in the design of power management systems. Usingconventional CMOS comparators, such as the one shown in Figure 1 , leads to complications both in the design as well as the layout,in order to keep offsets to a minimum. Auto-zeroing comparators canbe used to keep system offsets to a minimum and improve theperformance of the regulator system.

Figure 1: Conventional PMOS input-comparator design
(Click on image to enlarge)


R DSON Sensing Comparator
An important function of a voltage-regulator system is the abilityto maximize power efficiency at various levels of load currents.One way of achieving this is for the regulator to know when it isrunning in the low-power, variable-frequency pulse mode duringdiscontinuous conduction operation (inductor current goes to zero)and when to change into the fixed-frequency PWM mode for operationin the continuous conduction region (inductor current is alwaysgreater than zero).

During the variable-frequency operation mode, the regulator willoutput pulses in response to the ripple current through theinductor. This mode of operation is used during low current loadingbecause the low-side FET can be turned off when the reverse currentthrough the inductor is allowed to go to zero. At low currentlevels this mode of operation is more efficient than the PWM mode.A hysteretic comparator is used to compare the output voltage to areference plus some degree of hysteresis. As the current loadincreases, the frequency of the control pulses increases as theoutput crosses the hysteresis threshold more frequently.

One of the problems with this architecture is that the system mustbe able to determine when the inductor current enters into thediscontinuous-conduction mode of operation. This can beaccomplished by placing a comparator that looks across the switch node, SW, and compares the voltage across the drain-source node ofthe low side FET with ground.

Figure 2 shows a block diagram of a typical application for a SW node RDSONsensing comparator.

Figure 2: SW node comparator application
(Click on image to enlarge)


In the figure, Transistor M1 is the high-side MOSFET and transistorM2 is the low-side MOSFET. As the inductor current passes throughzero and becomes negative during the time that the low-side FET M2is turned on, the voltage on the drain of the FET becomes positive.

The comparator senses this change, and reports back to the systemthat a discontinuous event has occurred. Most systems will countthe number of times that this comparator reports this condition andafter perhaps eight counts, the system will change modes. However,this type of a comparison for a conventional CMOS comparator(Figure 1) is a difficult challenge. The comparator must be able torespond to a few millivolts of input signal from the drain of thelow-side FET in the presence of large amounts of ground noise.

If we take the example of a PWM regulator with a nominal outputcurrent of 5 A, we would like to set the discontinuous modetransition to begin at 0.1 × I OUT , or 0.5 A. If we choose a low-side power MOSFET with an R DSON of 40 mΩ, then the comparator will be looking at a signal of0.5 A/2 × 0.04 = 10 mV. For CMOS integrated-circuitcomparators, offsets can easily be in the 8 to 12-mV range orhigher, depending on the layout. This variation will cause a widedistribution in where the controller senses the crossover pointbetween continuous conduction and discontinuous conduction regionsof operation, thus leading to possible yield loss.

Designing a conventional CMOS comparator to handle this jobrequires offset trimming and very careful layout. This type ofcomparator application is well-suited to an auto-zeroingcomparator. Figure 3 shows a simplified schematic of an auto-zeroing comparator.

Figure 3: Simplified auto-zeroing comparator
(Click on image to enlarge)


The auto-zero comparator circuit is controlled by the DRIVE signal.During the auto-zeroing phase of operation, DRIVE is high and MN1is connected across C1 by closing switch S1 and connecting switchS2 to ground. During this time, the voltage of MN1 is stored acrossthe storage capacitor C1.

During the sampling phase of operation, the DRIVE signal is low andswitch S1 is open and switch S2 now becomes connected to the inputnode, SW. When SW is below zero volts, MN1 is pinched off by thevoltage on C1, allowing I1 to pull up on the drain of MN1. Once SWcrosses zero volts, MN1 turns on and begins to pull down the gateof MN2, thus causing the COMPOUT node to change state.

The obvious advantage of this circuit is to null the part-to-partvariations in the offset of transistor MN1. The advantage of thiscircuit is that the input to the comparator is connected to groundduring the noisy transition between the high-side power FET turningoff and the low-side power FET turning on. The DRIVE signal is onlychanged to the sample mode when the low side FET is in the full-oncondition.

A further advantage of this architecture is that the comparatorinput is disconnected from the SW node during the time that thehigh-side FET is on. In a portable computer application, the SWnode voltage could go as high as the charger output voltage ofaround 20 V. Using a conventional comparator, you would need toplace an additional high-voltage switch in series with thecomparator input in order to protect it.

( Part 2 of this article will look at the PWM comparator in more detail,and the resultant performance).

About the author
Stephen W. Bryson is a Principal Design Engineer at Fairchild Semiconductor Corp. San Jose, CA. He has published several papers and has patents inthe area of power management and drivers. He has a BSEE degree fromOregon State University and a MSEE from Santa Clara University.