Novel ferroelectric NAND flash memory cell demonstrates 10000 times

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Novel ferroelectric NAND flash memory cell demonstrates 10000 timesmore program and erase cycles than conventional memory cells Shigeki Sakai et al. of the Novel Electron Devices Group, theNanoelectronics Research Institute of the National Institute ofAdvanced Industrial Science and Technology (AIST) in collaborationwith Ken Takeuchi, Associate Professor of the Graduate School ofEngineering, the University of Tokyo have demonstrated that the useof ferroelectric gate field-effect transistors (FeFETs) as memorycells dramatically improves the performance of NAND flash memory.

The FeFET, the newly developed memory cell, can be programmed anderased as many times as 100 million or more and with programmingvoltage of less than 6 V, whereas the conventional NAND flashmemory cells have ten thousand program/erase endurance cycles withapproximately 20 V programming voltage. It has been assumed thatconventional NAND flash memory can be downsized to 30 nm at theminimum, whereas this novel memory cell will meet the needs of thenext 20-nm and 10-nm technology generations. And thus, this memorycell is expected to be used in a next-generation, high-density,high-capacity nonvolatile memory.

Results of the research was reported at the 23rd NonvolatileSemiconductor Memory Workshop (the 23rd IEEE NVSMW / the 3rd ICMTD2008) held in France, May 1822, 2008. Optical microscopic image of an FeFET for Fe-NAND flash memory. Thegate length and width are 3 µm and 50 µm, respectively.

As portable information devices have become increasingly widespreadin recent years, the need for smaller, lighter and lesspower-consuming data storage systems of high-capacity is growing.As a high-capacity data storage system, small, light andshock-proof solid state drives (SSDs) based on NAND flash memorieshave been attracting much attention these days instead of theconventional hard disk drive (HDD) which requires mechanical partssuch as a motor. Cost per bit of NAND flash memory is higher thanthat of the HDDs with magnetic disks. However, with efforts towardlowering the bit cost by increasing the cell density per unit area,the NAND flash memory has rapidly become popular in the market.

The NAND flash memory, however, can be programmed and erasedapproximately ten thousand times only, and further downsizing forincreasing the cell density will reduce the number of theprogram/erase endurance cycles and degrade the data reliability. Itis said that conventional memory cells cannot be downsized below 30nm process node because further downsizing will cause problems suchas capacitance coupling noise between the floating gates ofneighboring memory cells. The realization of using the FeFETs as memory cells in aferroelectric NAND (Fe-NAND) flash memory will not onlydramatically increase the number of program/erase endurance cycles,but also decrease the capacitance coupling noise betweenneighboring memory cells due to the absence of floating gates. Forthese reasons, the Fe-NAND is expected to be a high-density,high-capacity nonvolatile memory suitable for the future 20-nm and10-nm technology generations following the coming 30-nm. This research was conducted as a part of the "Development Projectof Nonvolatile Logic Circuit Board Technology for Low PowerConsumption Processors" under the "Efficient Energy UtilizationBasic Technology Pilot Research and Development Project" under the"Strategic Research and Development Project of Efficient EnergyUtilization Technology" of the New Energy and Industrial TechnologyDevelopment Organization.

First, an approximately 10-nm-thick high-permittivity dielectricHf-Al-O film, 400-nm-thick ferroelectric SrBi2Ta2O9 film, and then200-nm-thick platinum film were deposited in this order on a p-typeSi semiconductor substrate using a pulsed-laser depositiontechnique. The conditions of impurity doping to the channel areahad been adjusted so that the threshold voltage was optimized for aNAND flash memory cell. The gate, source, drain and substrateelectrodes were formed using the photolithography. And then, ann-channel FeFET with a metal-ferroelectric-insulator-semiconductor(MFIS) stacked gate structure was obtained.

An array structure of a Fe-NAND flash memory was assumed to be asshown in Fig. 2, and the appropriate voltage application conditionsthat enabled the data program, all erase, and readout operationswere carefully examined. Threshold voltages of the FeFET weremeasured after applying program and erase voltage pulses with avariety of pulse widths. The result was that the pulses with highspeed of 10 µs and low voltage of 6V worked enough forshowing two distinguishable threshold voltages which correspondedto the two different memorized states. The threshold voltages ofthe FeFET were measured also after applying program and erasedisturb voltages which were the voltages inevitably applied onunselected cells at the same time that the selected cells wereprogrammed and erased. As a result, we found out the appropriatevoltage application conditions for the unselected cells to avoidmemory errors by the program and erase disturbs.

Judging from the extrapolated lines drawn on the threshold-voltageretention curves of the program, erase, and program disturboperations, this n-channel FeFET was expected to retain the datafor as long as ten years. In addition, the threshold voltages didnot change significantly even after 100 million voltage pulses of10 µs and 6 V were applied for both data programming anderasing, indicating that the FeFET had more program/erase endurancecycles than 100 million times. In conclusion, we fabricated an n-channel FeFET for use as a memorycell in an Fe-NAND flash memory and demonstrated that the FeFET hadmore program/erase endurance cycles than 100 million times and lessoperation voltage than 6 volts. This memory cell is suitable for ahigh-density, high-capacity nonvolatile memory of 20-nm and 10-nmtechnology generations, which will not be realized by conventionalflash memories.