TI achieves best noise performance and dynamic range
http://www.fpgajournal.com/news_2008/06/20080623_0 [2008-6-27]
Tag : Analog Digital Clock
TI achieves best noise performance and dynamic range with new16-bit analog-to-digital converter and low-jitter clock combination
Solution delivers highest SNR and SFDR for demandingcommunications, defense, and test and measurement applications Texas Instruments Incorporated (TI)(NYSE:TXN) today introduced a 16-bit, single-channel, 135 megasamples per second (MSPS) analog-to-digital converter (ADC) and alow-jitter clock synthesizer. The combined signal chain solutionprovides unmatched dynamic system-level performance incommunications, defense, and test and measurement applications. Thedata converter and clock are available on the same evaluationmodule (EVM) to facilitate fast evaluations of these complexsystems.
Low noise enhances performance in wide-bandwidth applications
The ADS5483 ADC has the industry's highest signal-to-noise ratio(SNR) and spurious free dynamic range (SFDR) over comparable ADCson the market, for input frequencies from DC through the secondNyquist zone. Sampling at 135 MSPS, the ADC can achieve a SNR of78.6 dBFS with 95 dBc SFDR for a 70-MHz input frequency (IF), whichis up to 3.5 dB greater SNR or 8 dB greater SFDR over comparableADCs. The higher performance of the ADS5483 increases designflexibility and benefits many applications. For example, it offersgreater accuracy for test and measurement systems and highersensitivity with larger bandwidths in wireless communicationincluding air interfaces, such as WCDMA, TD-SCDMA, WiMAX, LTE andmulti-carrier 3GSM.
In wide-bandwidth applications, the ADS5483 eases analog front-enddesign by incorporating a fully differential input buffer, a commonfeature across TI's family of ADS54xx ADCs. Developed in TI'sBiCom3 high-speed process technology, this buffer provides constantinput impedance over input frequency and eliminates kickback fromthe ADC's track-and-hold structure to ensure consistent linearityof the signal. In addition, unlike competitive ADCs, the ADS5483utilizes differential double data rate (DDR) LVDS outputs tosignificantly reduce the number of I/O traces and pins it consumeson FPGA or ASIC devices.
Highly flexible clock enables system-level performance
The ultra-low jitter CDCE72010 clock synthesizer providesbest-in-class additive jitter performance at less than 50femtoseconds (fs), which meets the jitter requirements to clockhigh-speed ADCs, such as the ADS5483. For example, the combined EVMusing the CDCE72010 and a crystal band pass filter to drive theADS5483 at 122.8 MSPS achieves a high system-level SNR of 78.0 dBFSSNR and 89.1 dBc SFDR with a 100-MHz input frequency.
The new clock synthesizer can accommodate a wide range offrequencies to meet the requirements of various systems, such aswireless base stations or test and measurement equipment. It cansupport up to 10 LVPECL, 10 LVDS or 20 LVCMOS configurable outputsat frequencies up to 1.5 GHz and input frequencies from 8 KHz up to500 MHz. Designers can integrate two frequency sets within oneclock synthesizer with the option of two external VCO/VCXOs. TheCDCE72010's on-chip EEPROM stores default settings, which allowsdesigners to reduce system start-up time and eliminates the needfor an external component.
Tools and signal chain solutions ease development and enable rapidevaluation
The ADS5483 and the CDCE72010 are available on the same EVM tofacilitate fast evaluations of complex systems. To providedesigners with frequency planning flexibility, the EVM includes anopen socket for the VCXO and crystal filter as well as bypass foran external source clock input. TI also offers the TSW1200 digitalcapture tool, available across a wide portfolio of TI's high-speedLVDS-output ADCs. The TSW1200 enables rapid evaluation for ADCs ofup to 16-bit resolution and 500-MSPS sample rates to simplifydesign and help designers bring systems to market faster.
To further ease design and speed time-to-market, TI offers a widevariety of devices to complete the signal chain, including thoselisted below.
TI achieves best noise performance and dynamic range with new16-bit analog-to-digital converter and low-jitter clock combination
Solution delivers highest SNR and SFDR for demandingcommunications, defense, and test and measurement applications Texas Instruments Incorporated (TI)(NYSE:TXN) today introduced a 16-bit, single-channel, 135 megasamples per second (MSPS) analog-to-digital converter (ADC) and alow-jitter clock synthesizer. The combined signal chain solutionprovides unmatched dynamic system-level performance incommunications, defense, and test and measurement applications. Thedata converter and clock are available on the same evaluationmodule (EVM) to facilitate fast evaluations of these complexsystems.
Low noise enhances performance in wide-bandwidth applications
The ADS5483 ADC has the industry's highest signal-to-noise ratio(SNR) and spurious free dynamic range (SFDR) over comparable ADCson the market, for input frequencies from DC through the secondNyquist zone. Sampling at 135 MSPS, the ADC can achieve a SNR of78.6 dBFS with 95 dBc SFDR for a 70-MHz input frequency (IF), whichis up to 3.5 dB greater SNR or 8 dB greater SFDR over comparableADCs. The higher performance of the ADS5483 increases designflexibility and benefits many applications. For example, it offersgreater accuracy for test and measurement systems and highersensitivity with larger bandwidths in wireless communicationincluding air interfaces, such as WCDMA, TD-SCDMA, WiMAX, LTE andmulti-carrier 3GSM.
In wide-bandwidth applications, the ADS5483 eases analog front-enddesign by incorporating a fully differential input buffer, a commonfeature across TI's family of ADS54xx ADCs. Developed in TI'sBiCom3 high-speed process technology, this buffer provides constantinput impedance over input frequency and eliminates kickback fromthe ADC's track-and-hold structure to ensure consistent linearityof the signal. In addition, unlike competitive ADCs, the ADS5483utilizes differential double data rate (DDR) LVDS outputs tosignificantly reduce the number of I/O traces and pins it consumeson FPGA or ASIC devices.
Highly flexible clock enables system-level performance
The ultra-low jitter CDCE72010 clock synthesizer providesbest-in-class additive jitter performance at less than 50femtoseconds (fs), which meets the jitter requirements to clockhigh-speed ADCs, such as the ADS5483. For example, the combined EVMusing the CDCE72010 and a crystal band pass filter to drive theADS5483 at 122.8 MSPS achieves a high system-level SNR of 78.0 dBFSSNR and 89.1 dBc SFDR with a 100-MHz input frequency.
The new clock synthesizer can accommodate a wide range offrequencies to meet the requirements of various systems, such aswireless base stations or test and measurement equipment. It cansupport up to 10 LVPECL, 10 LVDS or 20 LVCMOS configurable outputsat frequencies up to 1.5 GHz and input frequencies from 8 KHz up to500 MHz. Designers can integrate two frequency sets within oneclock synthesizer with the option of two external VCO/VCXOs. TheCDCE72010's on-chip EEPROM stores default settings, which allowsdesigners to reduce system start-up time and eliminates the needfor an external component.
Tools and signal chain solutions ease development and enable rapidevaluation
The ADS5483 and the CDCE72010 are available on the same EVM tofacilitate fast evaluations of complex systems. To providedesigners with frequency planning flexibility, the EVM includes anopen socket for the VCXO and crystal filter as well as bypass foran external source clock input. TI also offers the TSW1200 digitalcapture tool, available across a wide portfolio of TI's high-speedLVDS-output ADCs. The TSW1200 enables rapid evaluation for ADCs ofup to 16-bit resolution and 500-MSPS sample rates to simplifydesign and help designers bring systems to market faster.
To further ease design and speed time-to-market, TI offers a widevariety of devices to complete the signal chain, including thoselisted below.
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